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The lab schedules for EECS168 at UC Riverside

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eecs168 - Introduction to VLSI Design

Lab Resources

Every discussion/Q&A will be at Please use GITHUB page instead of email to ask any questions to TA. Questions of confidential nature, eg. grading, are the exception. Labs must be finished on the given time. You have one week for your lab report. Lab due dates are indicated in the Lab schedule. Your lab will be due on your respective lab day (except Lab 4), eg. if your lab day is Wednesday then you will turn in your lab on the Wednesday of the week your lab is due. Please be sure to include all required deliverables in your lab report. Four lab reports are required to turn in and total score is 100.

Lab schedule

| Week | Date | Remark | Description Points | | ---- | ---- | -------| ------------------ | | Week 1 | Pre-Lab - ENGR account checkup / Linux System Basic | | | | Week 2 | Lab/Tutorial 1 - Synopsys Schematic Design (Galaxy Custom Designer)/ Pre-Simulation (HSPICE) | |20| | Week 3 | Lab/Tutorial 2 - Synopsys Layout Design (Galaxy Custom Designer) / Design Rule Check (DRC) / Verification (LVS) | Lab1 report due by the beginning of lab | 25 | |Week 4 | Lab/Tutorial 3 - Post-Simulation with Parasitic Extraction (HSPICE). Simple Hierarchical IC Design (Target Circuit: Ring Oscillator) | Lab2 report due by the beginning of lab. | 30 | |Week 5 | Lab/Tutorial 3 - Hierarchical IC Design (Target Circuit: 1-bit full adder-no hierarchical design) | | | |Week 6 | Lab/Tutorial 3 - Hierarchical IC Design (Target Circuit: 4-bit full adder-use Hierarchical) | | | |Week 7 | Lab3 work week. No new assignment. | | | |Week 8 | Lab/Tutorial 4 - RTL Synthesis Design (Design Compiler/IC Compiler/PrimeTime) (Target Circuit: 4-bit full adder)|Lab3 report due by the beginning of lab.| 25 | |Week 9 | Lab/Tutorial 4 - Complex RTL Synthesis Design (Target Circuit: Euclid's Algorithm for GCD)| | | |Week 10 | No lab | | Lab4 report due by Friday. | |Final Week | No lab | | | |

Attendance Policy

Lab attendance is not mandatory if you have finished the lab prior to the lab time.

Late Submission for lab report

  • Late submission will be 50% penalty.


  • You need to get checkoff your each lab result by video. If not , you will receive no credit for your lab score even if you submit your lab report. Checkoff by video means recording the results of running simulation and displaying the output waveforms in the video. Upload the video to googledrive/youtube and put the link at the top of your lab report.

Cheating Policy

Each lab report should be individual even if you can do pair design and programming. If I find students cheating on the lab report, I give no credit for lab given report. Then I forward your case to the academic integrity board at UCR.

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