Need help with ucr-eecs168-lab?
Click the “chat” button below for chat support from the developer who created it, or find similar developers for support.

About the developer

sheldonucr
208 Stars 20 Forks 164 Commits 65 Opened issues

Description

The lab schedules for EECS168 at UC Riverside

Services available

!
?

Need anything else?

Contributors list

No Data

eecs168 - Introduction to VLSI Design

Lab Resources

Every discussion/Q&A will be at https://github.com/sheldonucr/ucr-eecs168-lab. Please use GITHUB page instead of email to ask any questions to TA. Questions of confidential nature, eg. grading, are the exception. Labs must be finished on the given time. You have one week for your lab report. Lab due dates are indicated in the Lab schedule. Your lab will be due on your respective lab day (except Lab 4), eg. if your lab day is Wednesday then you will turn in your lab on the Wednesday of the week your lab is due. Please be sure to include all required deliverables in your lab report. Four lab reports are required to turn in and total score is 100.

Lab schedule

| Week | Date | Remark | Description Points | | ---- | ---- | -------| ------------------ | | Week 1 | Pre-Lab - ENGR account checkup / Linux System Basic | | | | Week 2 | Lab/Tutorial 1 - Synopsys Schematic Design (Galaxy Custom Designer)/ Pre-Simulation (HSPICE) | |15| | Week 3 | Lab/Tutorial 2 - Synopsys Layout Design (Galaxy Custom Designer) / Design Rule Check (DRC) / Verification (LVS) | Lab1 report due by the beginning of lab | 20 | |Week 4 | Lab/Tutorial 3 - Post-Simulation with Parasitic Extraction (HSPICE). Simple Hierarchical IC Design (Target Circuit: Ring Oscillator) | Lab2 report due by the beginning of lab. | 40 | |Week 5 | Lab/Tutorial 3 - Hierarchical IC Design (Target Circuit: 1-bit full adder-no hierarchical design) | | | |Week 6 | Lab/Tutorial 3 - Hierarchical IC Design (Target Circuit: 4-bit full adder-use Hierarchical) | | | |Week 7 | Lab3 work week. No new assignment. | | | |Week 8 | Lab/Tutorial 4 - RTL Synthesis Design (Design Compiler/IC Compiler/PrimeTime) (Target Circuit: 4-bit full adder)|Lab3 report due by the beginning of lab.| 25 | |Week 9 | Lab/Tutorial 4 - Complex RTL Synthesis Design (Target Circuit: Euclid's Algorithm for GCD)| | | |Week 10 | No lab | | Lab4 report due by Friday. | |Final Week | No lab | | | |

Attendance Policy

  • Late will be 10% penalty.
  • Missing a lab is acceptable only for emergency (eg. Medical emergency, doctor letter is required) and should be completed within 1 week of the missed lab.
  • Labs can be skipped by completing early. Proof of completion will be due prior to the start of your scheduled lab day. Available by request ONLY.

Late Submission for lab report

  • Late submission will be 50% penalty.

Checkoff

  • You need to get checkoff your each lab result. If not , you will receive no credit for your lab score even if you submit your lab report. Checkoff means showing your completed work to your TA.

Cheating Policy

Each lab report should be individual even if you can do pair design and programming. If I find students cheating on the lab report, I give no credit for lab given report. Then I forward your case to the academic integrity board at UCR.

We use cookies. If you continue to browse the site, you agree to the use of cookies. For more information on our use of cookies please see our Privacy Policy.