FPGA/hardware design of openwifi
openwifi: Linux mac80211 compatible full-stack IEEE802.11/Wi-Fi design based on SDR (Software Defined Radio).
This repository includes Hardware/FPGA design. To be used together with openwifi driver and software repository.
Openwifi code has dual licenses. AGPLv3 is the opensource license. For non-opensource license, please contact [email protected] Openwifi project also leverages some 3rd party modules. It is user's duty to check and follow licenses of those modules according to the purpose/usage. You can find an example explanation from Analog Devices for this compound license conditions. [How to contribute].
Pre-compiled FPGA files: boards/board_name/sdk/ has FPGA bit file, ila .ltx file and some other files might be needed.
board_name options: - zc706_fmcs2 (Xilinx ZC706 dev board + FMCOMMS2/3/4) - zed_fmcs2 (Xilinx zed board + FMCOMMS2/3/4) - adrv9361z7035 (ADRV9361-Z7035 + ADRV1CRR-BOB/FMC) - adrv9364z7020 (ADRV9364-Z7020 + ADRV1CRR-BOB) - zc702_fmcs2 (Xilinx ZC702 dev board + FMCOMMS2/3/4) - zcu102_fmcs2 (Xilinx ZCU102 dev board + FMCOMMS2/3/4)
Build FPGA: (Xilinx Vivado (also SDK and HLS) 2018.3 is needed. Example instructions are verified on Ubuntu 18)
export XILINX_DIR=your_Xilinx_directory ./prepare_adi_lib.sh $XILINX_DIR
./prepare_adi_board_ip.sh $XILINX_DIR $BOARD_NAME (Don't need to wait till the building end. When you see "Building ABCD project [...", you can stop it.)
Change to openwifi-hw/boards/board_name/ directory by "cd" command, if Vivado is launched in different directory. source ./openwifi.tcl
Open Block Design Tools --> Report --> Report IP Status Generate Bitstream (Will take a while) File --> Export --> Export Hardware... --> Include bitstream --> OK File --> Launch SDK --> OK, then close SDK
cd openwifi-hw/boards ./sdk_update.sh board_name git commit -a -m "new fpga img for openwifi (or comments you want to make)" git push (Above make sure you can pull this new FPGA from openwifi submodule directory: openwifi-hw)Modify IP cores:
IP core source files are in "ip" directory. After IP is modified, export the IP core into "iprepo" directory. Then re-run the full FPGA build procedure. For IP project created by **high.tcl** or _low.tcl or ultrascale.tcl, exporting target directory should be ip_repo/high/ or ip_repo/low/ or iprepo/ultrascale/ (for ZynqMP SoC, like zcu102 board). Other IP should be exported to ip_repo/common/.
Create a project "mixer_ddc" with file in ip/mixer_ddc/src directory in Vivado HLS. During creating, set mixer_ddc as top, select zc706 board as "Part" and set Clock Period 5 (means 200MHz). Run C synthesis. Click solution1, Solution --> Export RTL Copy project_directory/solution1/impl/ip to ip_repo/common/mixer_ddc
Open Vivado, then in Vivado Tcl Console: cd ip/fifo32_1clk source ./fifo32_1clk.tcl In Vivado: Open Block Design Tools --> Report --> Report IP Status Tools --> Create and Package New IP... --> Next --> Package a block design from ... --> Next --> set "ip_repo/common/fifo32_1clk" as target directory --> Next --> OK -- Finish In new opened temporary project: Review and Package --> Package IP --> Yes
Open Vivado, then in Vivado Tcl Console: cd ip/xpu source ./xpu_high.tcl In Vivado: Tools --> Report --> Report IP Status Tools --> Create and Package New IP... --> Next --> Next --> set "ip_repo/high/xpu" as target directory --> Next --> OK -- Finish In new opened temporary project: Review and Package --> Package IP --> Yes
openofdm_rx: You need to apply the evaluation license of Xilinx Viterbi Decoder and install on your PC firstly.
cd ip/ git submodule init openofdmrx git submodule update openofdmrx cd openofdm_rx git checkout dot11zynq git pull
Open Vivado, then in Vivado Tcl Console:
cd ip/openofdmrx source ./openofdmrx.tcl
Tools --> Report --> Report IP Status Tools --> Create and Package New IP... --> Next --> Next --> set "iprepo/common/openofdmrx" as target directory --> Next --> OK -- Finish In new opened temporary project: Review and Package --> Package IP --> Yes
Note: openwifi adds necessary modules/modifications on top of Analog Devices HDL reference design. For general issues, Analog Devices wiki pages would be helpful!