BaseJump STL: A Standard Template Library for SystemVerilog
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This library is a comprehensive hardware library for SystemVerilog that seeks to contain all of the commonly used HW primitives.
See this paper docs/BaseJumpSTLDAC2018Camera_Ready.pdf which describes the design and usage.
To use BaseJump STL, you currently need to specify bsgmisc/bsgdefines.v as a pre include file for your simulation or simulation toolsuite.
It defines a bunch of macros that are used across BaseJump STL.
Small, miscellaneous building blocks, like counters, reset timers, gray to binary coders, etc.
This is for asynchronous building blocks, like the bsgasyncfifo, synchronizers, and credit counters.
Bsg front side bus modules; also murn interfacing code.
Unidirectional off-chip high-speed source synchronous communication interface. (also used as FPGA bridge).
For standalone modules involved in data plumbing. E.g. two-element fifos, fifo-to-fifo transfer engines, sbox units, compareandswap, and array pack/unpack.
Data, clock, and reset generator for test benches.
Mirrors the other directories, with tests.
Mirrors other directories, contains replacement files for specific process technologies.
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