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BaseJump STL: A Standard Template Library for SystemVerilog

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BaseJump Standard Template Library (STL) Repository

This library is a comprehensive hardware library for SystemVerilog that seeks to contain all of the commonly used HW primitives.

See this paper docs/BaseJumpSTLDAC2018Camera_Ready.pdf which describes the design and usage.

Please also see the BSG SystemVerilog Style Guide which describes many of the conventions used in this library, including the variants of the valid/ready handshaking protocols.


  • bsg_misc

Small, miscellaneous building blocks, like counters, reset timers, gray to binary coders, etc.

  • bsg_async

This is for asynchronous building blocks, like the bsgasyncfifo, synchronizers, and credit counters.

  • bsg_fsb

Bsg front side bus modules; also murn interfacing code.

  • bsg_link

Unidirectional off-chip high-speed source synchronous communication interface. (also used as FPGA bridge).

  • bsg_dataflow

For standalone modules involved in data plumbing. E.g. two-element fifos, fifo-to-fifo transfer engines, sbox units, compareandswap, and array pack/unpack.

  • bsg_test

Data, clock, and reset generator for test benches.

  • testing

Mirrors the other directories, with tests.

  • hard

Mirrors other directories, contains replacement files for specific process technologies.


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